----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:09:09 11/06/2010 
-- Design Name: 
-- Module Name:    Gateway - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Gateway is
    Port ( tdi : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           shift : in  STD_LOGIC;
           update : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           wsoi : in  STD_LOGIC;
           sel : out  STD_LOGIC;
           wsio : out  STD_LOGIC;
           tdo : out  STD_LOGIC);
end Gateway;

architecture Behavioral of Gateway is

signal inreg0, inreg1, outreg0, outreg1 : std_logic;
component mux is
    Port ( in0 : in  STD_LOGIC;
           in1 : in  STD_LOGIC;
			  sel : IN std_logic;
           out0 : out  STD_LOGIC);
end component;

component FF is
    Port ( fin : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           fout : out  STD_LOGIC;
			  clk : in STD_LOGIC);
end component;

begin
      wsio <= outreg0;
	  sel <= outreg1;
	  
	  mux0 : mux 
      port map (outreg0, tdi, shift, inreg0);
		
	  FF0: FF
      port map(inreg0, reset, outreg0, clk);	

     mux1: mux	
		port map (outreg1, outreg0, update, inreg1);
		
	  FF1: FF
		port map(inreg1, reset, outreg1, clk);
		
	  mux2: mux
		port map (outreg0, wsoi, outreg1, tdo);

		
end Behavioral;

